Cad Wiki for Analog IC Courses

Login to the ECE Linux VM cpeg424.ece.udel.edu using the VNC Client.

1) Open the .bashrc file in your home directory. If it doesn't exist already, then create one using a text editor such as gedit

cd
gedit .bashrc &

Add the following lines to the .bashrc file in your home directory.

export CDSDIR=/software/Cadence/IC618
export CDK_DIR=/usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta
export MMSIM_PATH=/software/Cadence/SPECTRE191
export PATH=$PATH:$CDSDIR/tools/bin
export PATH=$PATH:$CDSDIR/tools/dfII/bin
export PATH=$PATH:$CDSDIR/tools/lib/64bit
export PATH=$PATH:$MMSIM_PATH/bin
export PATH=$PATH:$MMSIM_PATH/tools/bin
export PATH=$PATH:$MMSIM_PATH/tools/lib

# Add this line, otherwise LVS will not work
export CDS_Netlisting_Mode="Analog"

# Add this line so that ADE works on our 64-bit machine
export CDS_AUTO_64BIT=ALL

Save the above file. Then in the command line, refresh the bash shell

source .bashrc

2) Copy the .cdsenv file into your home directory. Please be mindful of the dot, i.e. “.”, in the filename

cp    /usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta/cdssetup/cdsenv  .cdsenv

3) Create and descend into your course work directory, e.g. analog_course. Better create a new directory for every course you take.

cd
mkdir analog_course
cd analog_course

4) If you have existing files, save backups of the files below, otherwise skip this step

cp .cdsinit  .cdsinit_bkp 
cp cds.lib  cds.lib_bkp 

5) Copy the .cdsinit from the NCSU setup directory using the command below to your into the analog_course directory. Again, be mindful of the dot, i.e. “.”, in the filename

cp    /usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta/cdssetup/cdsinit  .cdsinit

6) If you don't have an existing cds.lib file, then copy the cds.lib file using the following command:

cp    /usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta/cdssetup/cds.lib  cds.lib

7) You should be ready to start Cadence Virtuoso now! Always start virtuoso from your analog_course directory (and not the home directory)

virtuoso &

This completes your Cadence setup for the CPEG 424/624 course. You can move on to the Cadence Video Tutorials now.

180nm CMOS models are located in the following directory on the VM server.

 /usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta/models/spectre/standalone 

tsmc018allModels.scs : 180nm CMOS models with tt, ss, sf, fs and ff process corners.

The 1um and 50nm CMOS models are located in the following directory on the VM server.

 /usa/vsaxena/pdks/models/ 

cmos_1u.txt: 1um CMOS models

cmos_50n.txt: 50nm CMOS models

We are using a 0.18 micron 6 Metal 1 Poly (1.8V) CMOS technology for chip layout. In PDK specific terms, we will use SUBM_DEEP design rules with lambda(λ) equal to 0.09 micro meters with Lmin=2λ. Note that this λ is not the channel length modulation parameter!

The design rules are available as a PDF and also in Web Browsable Format.

Note that the design rules are given in terms of λ while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.09u for final layout dimensions. E.g. the minimum N-well width of 12 translates into 12*0.09u=1.08u in Virtuoso layout.

The process characterization results are available as: tsmc018_info.pdf. You can find numerical values for the various resistances and capacitances in the process.

If you are interested, you may add Prof. Baker's CMOS book examples by adding the following line to your cds.lib file

SOFTINCLUDE /usa/vsaxena/CMOSedu/CMOS_cds.lib

Note: Please do not re-download Prof. Baker's CMOS Book examples from http://cmosedu.com and/or install the NCSU PDK as directed in the CMOSEdu tutorials. They are already installed and available in your course directory and can be seen in the Cadence Library Manager.