Cad Wiki for Analog IC Courses

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Cadence Setup for ECE 445: Introduction to VLSI Design

Login to the ENGR server ece-ecegrad.ece.uidaho.edu using X2Go+Mate Client. Linux and Mac users can use ssh instead of the X2Go client. They can do this with

 ssh -XY [username]@ece-ecegrad.ece.uidaho.edu

This page will be modified/edited as we go along the semester to improve the simulation experience. Thus, its a good idea to check it if you run into problems.

Setting up NCSU Library

0) Open the .bashrc file in your home directory

cd
gedit .bashrc

Add the following lines to the .bashrc file in your home directory

export CDSDIR=/usr/local/cadence/installs/IC617
export CDK_DIR=/home/vsaxena/pdk/ncsu-cdk-1.6.0.beta

Refresh the bash shell

source .bashrc

1) Copy the .cdsenv file into your home directory.

cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/.cdsenv  .cdsenv

2) Create and go to your course work directory e.g. ece445. Better create a new directory for every course.

cd
mkdir ece445

Change your directory permissions by using the chmod command. Make sure that others are not able to read your files.

cd ..
chmod  –R  700  ece445

Enter the ece445 directory.

cd ece445

3) If you have existing files, save backups of the files below

cp .cdsinit  .cdsinit_bkp 
cp cds.lib  cds.lib_bkp

4) Copy .cdsinit from the NCSU setup directory using the command below to your into ece445 directory

cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/.cdsinit  .cdsinit

Make sure you have this .cdsinit file copied into the ece445 folder.

5) If you dont have an existing cds.lib file, then copy the cds.lib file using the following command and skip to the next step:

cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/cds.lib  cds.lib

Please note that we are using 0.5um On-Semi CMOS models while using NCSU libraries. This may be different from some of the tutorials and setup used in other courses.

6) You should be ready to start Cadence Virtuoso now!

virtuoso &

CMOS Book Examples

You can add CMOS book examples by adding the following line to your cds.lib file. These are already included in the cds.lib file that you've already copied in Step 5.

SOFTINCLUDE /home/vsaxena/CMOSedu/cds.lib

You can comment this line in the cds.lib file if you don't want to clutter up your Library Manager view with the examples.

Please do not re-download Prof Baker's CMOS Book examples from http://cmosedu.com and/or install the NCSU PDK as directed in the CMOSEdu tutorials. They are already installed and available in your course directory and can be seen in the Cadence Library Manager.

Running Book Examples

Basic instructions for simulating CMOS book examples using Cadence Spectre (refer to the Cadence Tutorials for details):

With Cadence running use the Library Manager to open the schematic view of a cell for simulation using Virtuoso Schematic Editor (SE)
In the menu of the SE Window select Launch → ADE L to open the Virtuoso Analog Design Environment (ADE) Window. Use the ‘Always’ option when prompted for license.
In the ADE Window’s menu select Setup → Simulator/Directory/Host… and then set the Simulator menu item
- For most simulations Spectre will be used, if UltraSim or some other simulator is used it will be noted on the schematic. In your environment, Spectre should already be set up as the default simulator.
Next, again in the ADE Window’s menu, select Session → Load State
- set the Load State Option to Cellview and press OK
Finally, in the ADE Window’s menu select Simulation → Netlist and Run (or just hit the green button) to simulate.

Simulation Models

Simulation models are located in the following directory on the ECE servers.

 /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/models/spectre/nom

The course uses a combination of On-Semi C5 0.5um CMOS process that are named as ami06N.m for NMOS and ami06P.m for PMOS transistors.

C5 Design Rules and Process Information

Design information for the C5 0.5u process is available here.

Use the MOSIS Scalable CMOS (SCMOS) SUBM design rules for your ece510 layouts. The design rules can be found in this document. Note that the design rules are given in terms of lambda (=0.3u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.3u for final layout dimensions. Eg. the minimum N-well width of 12 translates into 12*0.3u=3.6u in Virtuoso layout.

Process information including sheet resistances, capacitances, and transistor parameters can be found here: amiprocess.pdf
The gate oxide capacitance Cox' is calculated as: Cox'=e0*eox/tox = (8.85 aF/um * 3.97)/14.1e-3 um = 2.5fF/um^2

Corner models for the C5 process are already available on the AMS server at the location

 /home/pdk/ncsu-cdk-1.6.0.beta/models/spectre/

In this directory, you should see 5 folders corresponding to each of the corner models: (nom)inal, (slow)-slow, (fast)-fast, slow_fast and fast_slow. Point to the models in these folders for your corner sims.

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