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Design Rules and Process Information for the NCSU 180nm CMOS PDK
Process Design Rules
We are using a 0.18 micron 6 Metal 1 Poly (1.8V) CMOS technology for chip layout. In PDK specific terms, we will use SUBM_DEEP design rules with lambda(λ) equal to 0.09 micro meters with Lmin=2λ. Note that this λ is not the channel length modulation parameter!
The design rules are available as a PDF and also in Web Browsable Format.
Note that the design rules are given in terms of λ while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.09u for final layout dimensions. E.g. the minimum N-well width of 12 translates into 12*0.09u=1.08u in Virtuoso layout.
Process Characterization Results
The process characterization results are available as: tsmc018_info.pdf. You can find numerical values for the various resistances and capacitances in the process.
