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ncsu_180nm_process_info
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Design Rules and Process Information for the NCSU 180nm CMOS Technology used in the class
We will be using an 0.18 micron 6 Metal 1 Poly (1.8V/3.3V) CMOS technology lambda(λ) equal to 0.09 micro meters.
We are using an open-source PDK from NCSU.
We will use the Scalable CMOS SUBM design rules for your layouts. Note that the design rules are given in terms of lambda (=0.09u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.09u for final layout dimensions. E.g. the minimum N-well width of 12 translates into 12*0.09u=1.08u in Virtuoso layout.
The scalable CMOS (SCMOS) design rules are also available in a web browsable format.
Process Parameters
ncsu_180nm_process_info.1599117587.txt.gz · Last modified: 2020/09/03 07:19 by vsaxena
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