Cad Wiki for Analog IC Courses

We will be using an 0.18 micron 6 Metal 1 Poly (1.8V/3.3V) CMOS technology lambda(λ) equal to 0.09 micro meters. We are using an open-source PDK from NCSU.

We will use the Scalable CMOS DEEP design rules for your CPEG 4/624 layouts. Note that the design rules are given in terms of lambda (=0.09u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.09u for final layout dimensions. E.g. the minimum N-well width of 12 translates into 12*0.09u=1.08u in Virtuoso layout.

We will be using the Scalable Deep Submicron CMOS rules for layout.

Design information for the C5 0.5u process is available here.

Process information including sheet resistances and transistor parameters can be found here .

Corner models for the C5 process are already available on the AMS server. They are usually located on the MOSIS site here.