Cad Wiki for Analog IC Courses

Design information for the C5 0.5u process is available here.

Use the MOSIS Scalable CMOS (SCMOS) SUBM design rules for your CPEG 4/624 layouts. The design rules can be found in this document. Note that the design rules are given in terms of lambda (=0.09u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.09u for final layout dimensions. Eg. the minimum N-well width of 12 translates into 12*0.09u=1.08u in Virtuoso layout.

Process information including sheet resistances and transistor parameters can be found here .

Corner models for the C5 process are already available on the AMS server. They are usually located on the MOSIS site here.