Table of Contents
Cadence Video Tutorials (Sky130 Technology)
Lab 1: Schematic Design and Simulation
- Schematic Design: Resistor Divider. Spectre DC operating point analysis, annotating node voltages (10:33)
- Schematic Design and Simulation: RC Circuit. Spectre AC and transient analysis (22:57)
- Hierarchical Schematic Design: Ideal Opamp Modeling. Hierarchical design and simulation. (23:13)
- MOSFET I-V Characterization: Plot I-V curves for the Skywater 130nm CMOS transistors. Parametric analysis. Using Calculator tool in ADE-L Slides.
The Sky130 CMOS models are located on the Linux server at
/usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta/models/spectre/standalone/tsmc018allModels.scs
Lab 2: Layout Basics
- Layout Basics. Layout layers, display options, setting up grid, overview of commands, and DRC rules (24:52)
- Layout: Poly Resistor. Layout of unsilicided poly resistor (10:02)
- Layout: Matched Voltage Divider. Design and layout of a matched voltage divider (26:15)
- Layout: MiM Capacitor. Layout of a MiM capacitor (12:17)
Lab 3: Bias Circuit Design
- See the Lab manual.
Lab 4: Diffamp Design
- See the Lab manual.
Digital Lab 1: CMOS Inverter and Ring Oscillator
- CMOS Inverter Design. Schematic and layout of a CMOS Inverter
- CMOS Inverter Simulation. Simulation of the CMOS Inverter
- Ring Oscillator Design. Schematic, layout and simulation of a ring oscillator using the CMOS inverter cell
Project: Create GDS File from Layout
- Using the Pad Frame
- Create GDS. Create GDS file from layout (6:13)
You can verify your tape-out GDS using Klayout which you can download (to be installed on your PC) from here. The layermap file for the tsmc02d technology is here (unzip it before use).
HW 2
- Schematic Design: Using 1um CMOS Models: Slides.
The 1um CMOS models are located on the Linux server at
/usa/vsaxena/models/CMOS_1u.txt