Cadence Bindkeys Cheat Sheet

NCSU PDK Design Rules (html site), scmos_180nm.pdf (PDF doc)

NCSU 180nm CMOS Process Data

• Schematic Design: Resistor Divider. Spectre DC operating point analysis, annotating node voltages (10:33)

• Schematic Design and Simulation: RC Circuit. Spectre AC and transient analysis (22:57)

• Hierarchical Schematic Design: Ideal Opamp Modeling. Hierarchical design and simulation. (23:13)

• MOSFET I-V Characterization: Plot I-V curves for the 180nm CMOS transistors in NCSU PDK. Parametric analysis. Using Calculator tool in ADE-L (26:05) Slides.

The 180nm CMOS models are located on the Linux server at

  /usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta/models/spectre/standalone/tsmc018allModels.scs 

• Layout Basics. Layout layers, display options, setting up grid, overview of commands, and DRC rules (24:52)
• Layout: Poly Resistor. Layout of unsilicided poly resistor (10:02)
• Layout: Matched Voltage Divider. Design and layout of a matched voltage divider (26:15)
• Layout: MiM Capacitor. Layout of a MiM capacitor (12:17)

• See the Lab manual.

• See the Lab manual.

• CMOS Inverter Design. Schematic and layout of a CMOS Inverter
• CMOS Inverter Simulation. Simulation of the CMOS Inverter
• Ring Oscillator Design. Schematic, layout and simulation of a ring oscillator using the CMOS inverter cell
• Using Iterative Nets in Cadence

• Using the Pad Frame
• Create GDS. Create GDS file from layout (6:13)

You can verify your tape-out GDS using Klayout which you can download (to be installed on your PC) from here. The layermap file for the tsmc02d technology is here (unzip it before use).

• Schematic Design: Using 1um CMOS Models: Slides.

The 1um CMOS models are located on the Linux server at

 /usa/vsaxena/models/CMOS_1u.txt