==== C5 Design Rules and Process Information ====

  * **Design information** for the C5 0.5u process is available [[http://www.mosis.com/vendors/view/on-semiconductor/c5|here]].

  * Use the MOSIS Scalable CMOS (SCMOS) **SUBM** **design rules** for your ece510 layouts. The design rules can be found in this [[http://www.mosis.com/files/scmos/scmos.pdf|document]]. Note that the design rules are given in terms of lambda (=0.3u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.3u for final layout dimensions. Eg. the minimum N-well width of 12 translates into 12*0.3u=3.6u in Virtuoso layout.

  * **Process information** including sheet resistances and transistor parameters can be found {{ :wiki:mosis_ami-c5-params.pdf |here}} . 



  * **Corner models** for the C5 process are already available on the AMS server. They are usually located on the MOSIS site [[http://www.mosis.com/files/test_data/ami_c5n_corner_bsim3.txt|here]].