===== Cadence Video Tutorials =====

{{:wiki:cadence_logo.png?200|}}

{{ :wiki:cadence_virtuoso_cheat_sheet.pdf |Cadence Bindkeys Cheat Sheet}}

 [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|NCSU PDK Design Rules ]] (html site), {{ :wiki:scmos_180nm.pdf |}} (PDF doc)

{{ :wiki:tsmc018_info_v2.pdf | NCSU 180nm CMOS Process Data}}

-----
==== Lab 1: Schematic Design and Simulation ====

  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Cadence_schematic_rdiv/Cadence_schematic_rdiv.html|Schematic Design: Resistor Divider]]. Spectre DC operating point analysis, annotating node voltages (10:33)

  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Cadence_schematic_RC/Cadence_schematic_RC.html|Schematic Design and Simulation: RC Circuit]]. Spectre AC and transient analysis (22:57)

  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Hierarchical_schematic_opamp/Hierarchical_schematic_opamp.html|Hierarchical Schematic Design: Ideal Opamp Modeling]]. Hierarchical design and simulation. (23:13)

  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/180nm_CMOS_IV_char/180nm_CMOS_IV_char.html|MOSFET I-V Characterization]]: Plot I-V curves for the 180nm CMOS transistors in NCSU PDK. Parametric analysis. Using  Calculator tool in ADE-L (26:05) {{ :wiki:180nm_cmos_simulation_setup.pdf |Slides}}.  

The 180nm CMOS models are located on the Linux server at <code>  /usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta/models/spectre/standalone/tsmc018allModels.scs </code>

-----

==== Lab 2: Layout Basics ====
  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_basics/Layout_basics.html|Layout Basics]]. Layout layers, display options, setting up grid, overview of commands, and DRC rules (24:52)
  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_poly_resistor/Layout_poly_resistor.html|Layout: Poly Resistor]]. Layout of unsilicided poly resistor (10:02)
  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/layout_voltage_divider/layout_voltage_divider.html|Layout: Matched Voltage Divider]]. Design and layout of a matched voltage divider  (26:15)
  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_mimcap/Layout_mimcap.html|Layout: MiM Capacitor]]. Layout of a MiM capacitor (12:17)

-----
==== Lab 3: Bias Circuit Design ====
  * See the Lab manual.

==== Lab 4: Diffamp Design ====
  * See the Lab manual.


----
==== Digital Lab 1: CMOS Inverter and Ring Oscillator ====
  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_design/cmos_inverter_design.html|CMOS Inverter Design]]. Schematic and layout of a CMOS Inverter  {{:wiki:inv_layout.png?40|}}
  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_simulation/cmos_inverter_simulation.html|CMOS Inverter Simulation]]. Simulation of the CMOS Inverter
  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/ring_oscillator_design/ring_oscillator_design.html|Ring Oscillator Design]]. Schematic, layout and simulation of a ring oscillator using the CMOS inverter cell {{:wiki:ring_osc_layout.png?100|}}
  * {{ :wiki:using_recursive_nets_in_cadence.pdf| Using Iterative Nets in Cadence}}

----

==== Project: Create GDS File from Layout ===
  * Using the [[Pad Frame]]              {{ :wiki:padframe1.png?200 |}}
  * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Create_GDS/Create_GDS.html|Create GDS]]. Create GDS file from layout (6:13)
{{:wiki:180n_layermap.png?300|}}

You can verify your tape-out GDS using **Klayout** which you can download (to be installed on your PC) from [[https://www.klayout.de/build.html|here]]. The layermap file for the tsmc02d technology is {{ :wiki:tsmc02d.zip |here}} (unzip it before use). 

----

==== HW 2 ====
  * Schematic Design: Using **1um CMOS Models**:  {{ :wiki:1um_cmos_simulation_setup.pdf |Slides}}. 

The 1um CMOS models are located on the Linux server at <code> /usa/vsaxena/models/CMOS_1u.txt </code>

-----