Cad Wiki for Analog IC Courses

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=====Cadence Setup for ECE 445: Introduction to VLSI Design =====

Graduate students login to the server **ece-ecegrad.ece.uidaho.edu** and undergraduates should log into Graduate students login to the server **ece-ece310.ece.uidaho.edu** using X2Go+Mate Client. 


Linux and Mac users can use ssh instead of the X2Go client.  They can do this with 

<code> ssh -XY [username]@ece-ecegrad.ece.uidaho.edu </code>

<note important>This page will be modified/edited as we go along the semester to improve the simulation experience. Thus, its a good idea to check it if you run into problems. </note>
 
==== Setting up NCSU Library ==== 

0) Open the .bashrc file in your home directory 
<code>
cd
gedit .bashrc
</code>

Add the following lines to the .bashrc file in your home directory
<code>
export CDSDIR=/usr/local/cadence/installs/IC617
# NCSU CDK specific
export SPECTRE_DEFAULTS=-E
export CDS_Netlisting_Mode=Analog
export CDS_LOAD_ENV=CWDElseHome
export CDK_DIR=/home/vsaxena/pdk/ncsu-cdk-1.6.0.beta
</code>

Refresh the bash shell
<code>
source .bashrc</code>

1) **Copy the .cdsinit, .cdsenv, .simrc and display.drf files** into your work directory i.e. ece445.
<code>
cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/cdsinit  .cdsinit
cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/cdsenv  .cdsenv
cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/simrc  .simrc
cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/display.drf  display.drf
</code>


2) Create and go to your course work directory e.g. ece445. Better create a new directory for every course.
<code>
cd
mkdir ece445
</code>

Change your directory permissions by using the chmod command. Make sure that others are not able to read your files. 
<code>
cd ..
chmod  –R  700  ece445
</code>

Enter the ece445 directory. 

<code>
cd ece445
</code>


<note warning>Make sure you have this .cdsinit file copied into the ece445 folder.</note>

3) If you don't have an existing cds.lib file, then copy the cds.lib file using the following command and skip to the next step:

<code>
cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/cds.lib  cds.lib
</code>

<note warning>Please note that we are using 0.5um On-Semi CMOS models while using NCSU libraries. This may be different from some of the tutorials and setup used in other courses.</note>

4) Create a symbolic link to CMOSEdu examples in your home directory
<code>
cd
ln -s /home/vsaxena/CMOSEdu
</code>


5) You should be ready to start Cadence Virtuoso now!

<code>
virtuoso &
</code>

===== Cadence Tutorials =====

Cadence tutorials using On Semi C5 process are posted [[http://lumerink.com/courses/ece445/Cadence_Tutorials/cadence_tutorials.htm|here]].

You can find the related Cadence libraries on the ece-ecegrad sever in my directory at  /home/vsaxena/ece445/
as **Tutorial_1** and **Layout_tutorial** libraries.


===== Simulation Models =====

==== Book Models ====
Book models are located at:

<code> /home/vsaxena/analog_design/models/ </code>

The 1um CMOS models are in the file cmosedu_models.text and the diode model is in the file diode2.txt.

==== On Semi C5 Models ====
Simulation models are located in the following directory on the ECE servers.

<code> /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/models/spectre/nom </code>

The course uses a combination of On-Semi C5 0.5um CMOS process that are named as ami06N.m for NMOS and ami06P.m for PMOS transistors. 
  

===== On Semi C5 Design Rules and Process Information =====

  * **Design information** for the C5 0.5u process is available [[https://www.mosis.com/vendors/view/on-semiconductor/c5|here]]. 

  * Use the MOSIS Scalable CMOS (SCMOS) **SUBM** **design rules** for your ece510 layouts. The design rules can be found in this [[http://mosis.com/files/scmos/scmos.pdf|document]]. Note that the design rules are given in terms of lambda (=0.3u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.3u for final layout dimensions. Eg. the minimum N-well width of 12 translates into 12*0.3u=3.6u in Virtuoso layout.

  * **Process information** including sheet resistances, capacitances, and transistor parameters can be found here: {{:wiki:amiprocess.pdf|}}
  * The gate oxide capacitance Cox' is calculated as: Cox'=e0*eox/tox = (8.85 aF/um * 3.97)/14.1e-3 um = 2.5fF/um^2


  * **Corner models** for the C5 process are already available on the AMS server at the location
   
        <code> /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/models/spectre/C5/  </code>
   
<note important>  In this directory, you should see 5 files corresponding to each of the corner models: (tt) typical, (ss)slow-slow, (ff) fast-fast, (sf) slow_fast and (fs) fast_slow. Point to the models in these files for your corner sims.
</note>

===== CMOS Book Examples =====
  * You can add CMOS book examples by adding the following line to your cds.lib file. These are already included in the cds.lib file that you've already copied in Step 5.

<code>
SOFTINCLUDE /home/vsaxena/CMOSedu/cds.lib
</code>

  * You can comment this line in the cds.lib file if you don't want to clutter up your Library Manager view with the examples.

<note warning>Please do not re-download Prof Baker's CMOS Book examples from http://cmosedu.com and/or install the NCSU PDK as directed in the CMOSEdu tutorials. They are already installed and available in your course directory and can be seen in the Cadence Library Manager.</note>

==== Running Book Examples ====
Basic instructions for simulating CMOS book examples using Cadence Spectre (refer to the Cadence [[http://cmosedu.com/videos/cadence/cadence_videos.htm|Tutorials]] for details):
  *   With Cadence running use the Library Manager to open the schematic view of a cell for simulation using Virtuoso Schematic Editor (SE)
  *   In the menu of the SE Window select Launch -> ADE L to open the Virtuoso Analog Design Environment (ADE) Window. Use the ‘Always’ option when prompted for license.
  *   In the ADE Window’s menu select Setup -> Simulator/Directory/Host… and then set the Simulator menu item
    * For most simulations Spectre will be used, if UltraSim or some other simulator is used it will be noted on the schematic. In your environment, Spectre should already be set up as the default simulator.
  * Next, again in the ADE Window’s menu, select Session -> Load State
    * set the Load State Option to **Cellview** and press OK
  * Finally, in the ADE Window’s menu select Simulation -> Netlist and Run (or just hit the green button) to simulate.
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