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| =====Cadence Setup for ECE 445: Introduction to VLSI Design ===== | =====Cadence Setup for ECE 445: Introduction to VLSI Design ===== | ||
| - | Login to the ENGR server **ece-ecegrad.ece.uidaho.edu** using X2Go+Mate Client. | + | Graduate students login to the server **ece-ecegrad.ece.uidaho.edu** and undergraduates should log into Graduate students login to the server **ece-ece310.ece.uidaho.edu** using X2Go+Mate Client. |
| + | |||
| Linux and Mac users can use ssh instead of the X2Go client. They can do this with | Linux and Mac users can use ssh instead of the X2Go client. They can do this with | ||
| Line 30: | Line 32: | ||
| source .bashrc</code> | source .bashrc</code> | ||
| - | 1) **Copy the .cdsinit, .cdsenv, .simrc and display.drf files** into your home directory. | + | 1) **Copy the .cdsinit, .cdsenv, .simrc and display.drf files** into your work directory i.e. ece445. |
| <code> | <code> | ||
| cp /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/cdsinit .cdsinit | cp /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/cdsinit .cdsinit | ||
| Line 88: | Line 90: | ||
| as **Tutorial_1** and **Layout_tutorial** libraries. | as **Tutorial_1** and **Layout_tutorial** libraries. | ||
| - | ===== CMOS Book Examples ===== | ||
| - | * You can add CMOS book examples by adding the following line to your cds.lib file. These are already included in the cds.lib file that you've already copied in Step 5. | ||
| - | |||
| - | <code> | ||
| - | SOFTINCLUDE /home/vsaxena/CMOSedu/cds.lib | ||
| - | </code> | ||
| - | |||
| - | * You can comment this line in the cds.lib file if you don't want to clutter up your Library Manager view with the examples. | ||
| - | |||
| - | <note warning>Please do not re-download Prof Baker's CMOS Book examples from http://cmosedu.com and/or install the NCSU PDK as directed in the CMOSEdu tutorials. They are already installed and available in your course directory and can be seen in the Cadence Library Manager.</note> | ||
| - | |||
| - | ==== Running Book Examples ==== | ||
| - | Basic instructions for simulating CMOS book examples using Cadence Spectre (refer to the Cadence [[http://cmosedu.com/videos/cadence/cadence_videos.htm|Tutorials]] for details): | ||
| - | * With Cadence running use the Library Manager to open the schematic view of a cell for simulation using Virtuoso Schematic Editor (SE) | ||
| - | * In the menu of the SE Window select Launch -> ADE L to open the Virtuoso Analog Design Environment (ADE) Window. Use the ‘Always’ option when prompted for license. | ||
| - | * In the ADE Window’s menu select Setup -> Simulator/Directory/Host… and then set the Simulator menu item | ||
| - | * For most simulations Spectre will be used, if UltraSim or some other simulator is used it will be noted on the schematic. In your environment, Spectre should already be set up as the default simulator. | ||
| - | * Next, again in the ADE Window’s menu, select Session -> Load State | ||
| - | * set the Load State Option to **Cellview** and press OK | ||
| - | * Finally, in the ADE Window’s menu select Simulation -> Netlist and Run (or just hit the green button) to simulate. | ||
| ===== Simulation Models ===== | ===== Simulation Models ===== | ||
| Line 126: | Line 108: | ||
| | | ||
| - | ==== C5 Design Rules and Process Information ==== | + | ===== On Semi C5 Design Rules and Process Information ===== |
| - | * **Design information** for the C5 0.5u process is available [[http://mosis.com/vendors/view/on-semiconductor/c5|here]]. | + | * **Design information** for the C5 0.5u process is available [[https://www.mosis.com/vendors/view/on-semiconductor/c5|here]]. |
| * Use the MOSIS Scalable CMOS (SCMOS) **SUBM** **design rules** for your ece510 layouts. The design rules can be found in this [[http://mosis.com/files/scmos/scmos.pdf|document]]. Note that the design rules are given in terms of lambda (=0.3u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.3u for final layout dimensions. Eg. the minimum N-well width of 12 translates into 12*0.3u=3.6u in Virtuoso layout. | * Use the MOSIS Scalable CMOS (SCMOS) **SUBM** **design rules** for your ece510 layouts. The design rules can be found in this [[http://mosis.com/files/scmos/scmos.pdf|document]]. Note that the design rules are given in terms of lambda (=0.3u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.3u for final layout dimensions. Eg. the minimum N-well width of 12 translates into 12*0.3u=3.6u in Virtuoso layout. | ||
| Line 142: | Line 124: | ||
| <note important> In this directory, you should see 5 files corresponding to each of the corner models: (tt) typical, (ss)slow-slow, (ff) fast-fast, (sf) slow_fast and (fs) fast_slow. Point to the models in these files for your corner sims. | <note important> In this directory, you should see 5 files corresponding to each of the corner models: (tt) typical, (ss)slow-slow, (ff) fast-fast, (sf) slow_fast and (fs) fast_slow. Point to the models in these files for your corner sims. | ||
| </note> | </note> | ||
| + | |||
| + | ===== CMOS Book Examples ===== | ||
| + | * You can add CMOS book examples by adding the following line to your cds.lib file. These are already included in the cds.lib file that you've already copied in Step 5. | ||
| + | |||
| + | <code> | ||
| + | SOFTINCLUDE /home/vsaxena/CMOSedu/cds.lib | ||
| + | </code> | ||
| + | |||
| + | * You can comment this line in the cds.lib file if you don't want to clutter up your Library Manager view with the examples. | ||
| + | |||
| + | <note warning>Please do not re-download Prof Baker's CMOS Book examples from http://cmosedu.com and/or install the NCSU PDK as directed in the CMOSEdu tutorials. They are already installed and available in your course directory and can be seen in the Cadence Library Manager.</note> | ||
| + | |||
| + | ==== Running Book Examples ==== | ||
| + | Basic instructions for simulating CMOS book examples using Cadence Spectre (refer to the Cadence [[http://cmosedu.com/videos/cadence/cadence_videos.htm|Tutorials]] for details): | ||
| + | * With Cadence running use the Library Manager to open the schematic view of a cell for simulation using Virtuoso Schematic Editor (SE) | ||
| + | * In the menu of the SE Window select Launch -> ADE L to open the Virtuoso Analog Design Environment (ADE) Window. Use the ‘Always’ option when prompted for license. | ||
| + | * In the ADE Window’s menu select Setup -> Simulator/Directory/Host… and then set the Simulator menu item | ||
| + | * For most simulations Spectre will be used, if UltraSim or some other simulator is used it will be noted on the schematic. In your environment, Spectre should already be set up as the default simulator. | ||
| + | * Next, again in the ADE Window’s menu, select Session -> Load State | ||
| + | * set the Load State Option to **Cellview** and press OK | ||
| + | * Finally, in the ADE Window’s menu select Simulation -> Netlist and Run (or just hit the green button) to simulate. | ||
| + | |||
| | | ||
vlsi_course.1549678634.txt.gz · Last modified: 2019/02/09 02:17 by vsaxena
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