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--- rfic [2018/09/23 07:30]
vsaxena
+++ rfic [2018/11/23 22:26] (current)
vsaxena [Setting up Cadence Libraries]
@@ Line 8: / Line 8: @@
 <note important>This page will be modified/edited as we go along the semester to improve the simulation experience. Thus, its a good idea to check it if you run into problems. </note>
-==== Setting up NCSU Library ====
+==== Setting up Cadence Libraries ====
 ) Open the .bashrc file in your home directory
@@ Line 18: / Line 18: @@
 Add the following lines to the .bashrc file in your home directory
 <code>
-export CDSDIR=/usr/local/cadence/installs/IC617
+export CDSHOME=/usr/local/cadence/installs/IC617
-export CDK_DIR=/home/vsaxena/pdk/ncsu-cdk-1.6.0.beta
+export CDS_Netlisting_Mode=Analog
 </code>
@@ Line 25: / Line 25: @@
 <code>
 source .bashrc</code>
-) Copy the .cdsenv file into your home directory.
-<code>
-cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/.cdsenv  .cdsenv
-</code>
-) Create and go to your course work directory e.g. ece515. Better create a new directory for every course.
+) Create and go to your course work directory e.g. ece513. Better create a new directory for every course.
 <code>
 cd
-mkdir ece515
+mkdir ece513
-cd ece515
+cd ece513
 </code>
-)  If you have existing files, save backups of the files below
+All work by the user should be performed in this circuit design directory. You can start Cadence Virtuoso by using the following command in your work directory.
 <code>
-cp .cdsinit  .cdsinit_bkp
+virtuoso &
-cp cds.lib  cds.lib_bkp
 </code>
-) Copy .cdsinit from the NCSU setup directory using the command below to your into ece515 directory
-<code>
+<note important>You should always start virtuoso in you ece513 course directory. </note>
-cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/.cdsinit  .cdsinit
-</code>
-<note warning>Make sure you have this .cdsinit file copied in the ece515 folder.</note>
-) If you dont have an existing cds.lib file, then copy the cds.lib file using the following command and skip to the next step:
+===== Creating a new Library =====
+The Library techfile contains all required techfile information.
+To create a new library that uses an attached techfile, use the command **File->New->Library** from either the CIW or library manager and select the **Attach to an existing techfile** option.
+For 45nm CMOS, select the **gpdk045** library when asked for the name of the Attach To Technology Library.
+When using model files directly (such as 90nm CMOS in this course), select the default **cdsDefTechLib** library when prompted to Attach To Technology Library.
+===== Simulation Models =====
+==== 45nm CMOS Models ====
+) Create a "cds.lib" file. Using any text editor the following entry should be put in the cds.lib file:
 <code>
-cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/cds.lib  cds.lib
+INCLUDE /home/vsaxena/pdk/gpdk045_v_5_0/cds.lib
 </code>
-If you have an existing cds.lib file, then merge the cds.lib file from (/home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cds.lib) with your existing cds.lib in the directory. This is equivalent to copying the following entries (note that CDK_DIR variable should be defined as in the first line below):
+) Use the command in the terminal to create a softlink to the models directory
 <code>
-# Include basic Spectre and Verilog-A libraries
+ln -s /home/vsaxena/pdk/gpdk045_v_5_0/models
-DEFINE basic    $CDSDIR/tools/dfII/etc/cdslib/basic
+</code>
-DEFINE analogLib $CDSDIR/tools/dfII/etc/cdslib/artist/analogLib
-DEFINE functional    $CDSDIR/tools/dfII/etc/cdslib/artist/functional
-DEFINE sbaLib    $CDSDIR/tools/dfII/etc/cdslib/artist/sbaLib
-DEFINE ahdlLib $CDSDIR/tools/dfII/samples/artist/ahdlLib
-DEFINE bmslib $CDSDIR/tools/dfII/samples/artist/bmslib
 ) You should be ready to start Cadence Virtuoso now!
 <code>
@@ Line 77: / Line 75: @@
 </code>
+) You can find the PDK documentation at
+<code>
+/home/vsaxena/pdk/gpdk045_v_5_0/docs
+</code>
-===== Simulation Models =====
+If you have setup everything correctly, simulation models should be automatically loaded. However, they can be found at:
-Simulation models are located in the following directory on the ece410.engr.uidaho.edu server.
+<code>
+/home/vsaxena/pdk/gpdk045_v_5_0/models
+</code>
-<code> /home/vsaxena/analog_design/models/ </code>
-We will use IBM 9SF **90nm** low-leakage CMOS Process courtesy Prof. Sankaran Aniruddhan from [[http://www.ee.iitm.ac.in/~ani/2013/ee6240/projects.html|IIT Madras]]. In the model noise parameters have been added manually from some other process.
+==== 90nm CMOS Models ====
+The **90nm CMOS models** are located in the /home.vsaxena/pdk/models/ibm90nm.scs file.
-The course uses a combination of long-channel (1um) and short-channel (180nm or 0.18um) CMOS models.
 You should instantiate the 'nbsim4' and 'pbsim4' devices from analogLib and point them to 'CMOSN' and 'CMOSP' models respectively. The above spectre model is all that you need to include in your simulation setup.
+==== Scalable Inductor Model ====
+The **scalable inductor model** is located on the server. Add the following line to the cds.lib file in your ece513 work directory
+<code>
+DEFINE RFIC2013 /home/vsaxena/pdk/models/RFIC2013
+</code>
+The cell to use is **ind_scale**. Use the simulation testbench tb_ind_scale to plot s-parameters for the inductor model. Read more in the textbook Chapter 4 on inductor modeling.
+{{:wiki:ind_scale.png?400|}}
 ===== Tutorials =====
 {{:wiki:tutorial_hw1_parametric_sweeps.pdf|I-V and Parametric Sweeps}} - Thanks to Jubayer!
+[[https://www.ece.ucsb.edu/Faculty/rodwell/Classes/ece218c/tutorials_etc/CadenceLNA.pdf|SpectreRF LNA Characterization Tutorial]]

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