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--- rfic [2018/08/13 11:25]
vsaxena created
+++ rfic [2018/11/23 22:26] (current)
vsaxena [Setting up Cadence Libraries]
@@ Line 1: / Line 1: @@
 =====Cadence Setup for ECE 5/413: Radio Frequency IC Design =====
-Login to the ENGR server **ece410.engr.uidaho.edu** using X2Go Client.
+Login to the ENGR server **ece-ecegrad.ece.uidaho.edu** using X2Go+Mate Client.
 Linux and Mac users can use ssh instead of the X2Go client.  They can do this with
-<code> ssh -XY [username]@ece410.engr.uidaho.edu </code>
+<code> ssh -XY [username]@ece-ecegrad.ece.uidaho.edu </code>
 <note important>This page will be modified/edited as we go along the semester to improve the simulation experience. Thus, its a good idea to check it if you run into problems. </note>
-==== Setting up NCSU Library ====
+==== Setting up Cadence Libraries ====
 ) Open the .bashrc file in your home directory
@@ Line 18: / Line 18: @@
 Add the following lines to the .bashrc file in your home directory
 <code>
-source /tools.new/cadence/setup/ic615
+export CDSHOME=/usr/local/cadence/installs/IC617
-export PATH=$PATH:/tools.new/examples/bin
+export CDS_Netlisting_Mode=Analog
 </code>
@@ Line 27: / Line 27: @@
-) Goto your work directory. Better create a new directory for every course.
+) Create and go to your course work directory e.g. ece513. Better create a new directory for every course.
 <code>
 cd
-mkdir ece515
+mkdir ece513
-cd ece515
+cd ece513
 </code>
-)  If you have existing files, save backups of the files below
+All work by the user should be performed in this circuit design directory. You can start Cadence Virtuoso by using the following command in your work directory.
 <code>
-cp .cdsinit  .cdsinit_bkp
+virtuoso &
-cp cds.lib  cds.lib_bkp
 </code>
-) Copy .cdsinit from instructor's directory using the command below to your into ece515 directory
-<code>
+<note important>You should always start virtuoso in you ece513 course directory. </note>
-cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/cdsinit  .cdsinit
-</code>
-) If you dont have an existing cds.lib file, then copy the cds.lib file using the following command and skip to the next step:
-<code>
+===== Creating a new Library =====
-cp    /home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cdssetup/cds.lib  cds.lib
-</code>
-If you have an existing cds.lib file, then merge the cds.lib file from (/home/vsaxena/pdk/ncsu-cdk-1.6.0.beta/cds.lib) with your existing cds.lib in the directory. This is equivalent to copying the following entries (note that CDK_DIR variable should be defined as in the first line below):
+The Library techfile contains all required techfile information.
-<code>
+To create a new library that uses an attached techfile, use the command **File->New->Library** from either the CIW or library manager and select the **Attach to an existing techfile** option.
-# NCSU Design Kit Path
-CDK_DIR = "/home/vsaxena/pdk/ncsu-cdk-1.6.0.beta"
-# Include basic Spectre and Verilog-A libraries
+For 45nm CMOS, select the **gpdk045** library when asked for the name of the Attach To Technology Library.
-DEFINE basic    $CDSDIR/tools/dfII/etc/cdslib/basic
-DEFINE analogLib $CDSDIR/tools/dfII/etc/cdslib/artist/analogLib
-DEFINE functional    $CDSDIR/tools/dfII/etc/cdslib/artist/functional
-DEFINE sbaLib    $CDSDIR/tools/dfII/etc/cdslib/artist/sbaLib
-DEFINE ahdlLib $CDSDIR/tools/dfII/samples/artist/ahdlLib
-DEFINE bmslib $CDSDIR/tools/dfII/samples/artist/bmslib
-# Include NCSU PDK
+When using model files directly (such as 90nm CMOS in this course), select the default **cdsDefTechLib** library when prompted to Attach To Technology Library.
-DEFINE basic $CDK_DIR/lib/basic
+===== Simulation Models =====
-DEFINE NCSU_Analog_Parts $CDK_DIR/lib/NCSU_Analog_Parts
-DEFINE NCSU_Digital_Parts $CDK_DIR/lib/NCSU_Digital_Parts
+==== 45nm CMOS Models ====
---DEFINE MOSIS_Layout_Test $CDK_DIR/lib/MOSIS_Layout_Test
-DEFINE NCSU_TechLib_ami06 $CDK_DIR/lib/NCSU_TechLib_ami06
+) Create a "cds.lib" file. Using any text editor the following entry should be put in the cds.lib file:
-DEFINE NCSU_TechLib_ami16 $CDK_DIR/lib/NCSU_TechLib_ami16
-DEFINE NCSU_TechLib_hp06 $CDK_DIR/lib/NCSU_TechLib_hp06
+<code>
-DEFINE NCSU_TechLib_tsmc02 $CDK_DIR/lib/NCSU_TechLib_tsmc02
+INCLUDE /home/vsaxena/pdk/gpdk045_v_5_0/cds.lib
-DEFINE NCSU_TechLib_tsmc02d $CDK_DIR/lib/NCSU_TechLib_tsmc02d
-DEFINE NCSU_TechLib_tsmc03 $CDK_DIR/lib/NCSU_TechLib_tsmc03
-DEFINE NCSU_TechLib_tsmc03d $CDK_DIR/lib/NCSU_TechLib_tsmc03d
-DEFINE NCSU_TechLib_tsmc04_4M2P $CDK_DIR/lib/NCSU_TechLib_tsmc04_4M2P
 </code>
-<note warning>Please note that we are using 1um and 180nm CMOS models while using NCSU libraries. This may be different from some of the tutorials and setup used in other courses.</note>
+) Use the command in the terminal to create a softlink to the models directory
+<code>
+ln -s /home/vsaxena/pdk/gpdk045_v_5_0/models
+</code>
 ) You should be ready to start Cadence Virtuoso now!
 <code>
@@ Line 90: / Line 75: @@
 </code>
-===== CMOS Book Examples =====
+) You can find the PDK documentation at
-You can add CMOS book examples by adding the following line to your cds.lib file
 <code>
-SOFTINCLUDE /home/vsaxena/CMOSedu/cds.lib
+/home/vsaxena/pdk/gpdk045_v_5_0/docs
 </code>
-<note warning>Please do not re-download Prof Baker's CMOS Book examples from http://cmosedu.com and/or install the NCSU PDK as directed in the CMOSEdu tutorials. They are already installed and available in your course directory and can be seen in the Cadence Library Manager.</note>
+If you have setup everything correctly, simulation models should be automatically loaded. However, they can be found at:
+<code>
+/home/vsaxena/pdk/gpdk045_v_5_0/models
+</code>
-===== Simulation Models =====
+==== 90nm CMOS Models ====
+The **90nm CMOS models** are located in the /home.vsaxena/pdk/models/ibm90nm.scs file.
-Simulation models are located in the following directory on the ece410.engr.uidaho.edu server.
+You should instantiate the 'nbsim4' and 'pbsim4' devices from analogLib and point them to 'CMOSN' and 'CMOSP' models respectively. The above spectre model is all that you need to include in your simulation setup.
-<code> /home/vsaxena/analog_design/models/ </code>
-The course uses a combination of long-channel (1um) and short-channel (180nm or 0.18um) CMOS models.
-The 1um models (in file cmosedu_models.txt) are for a closer matching to hand-calculations for some of the Homework problems, while 180nm models (in file  tsmc018.scs) provides a more realistic design experience in HWs and the project.
-==== Setting up the CMOS Simulation Models ====
+==== Scalable Inductor Model ====
-Please follow the instructions below to use the 180nm CMOS models. The method is same for using any other model e.g. 1um model. Its a good idea to open the model file and take a look at the contents.
+The **scalable inductor model** is located on the server. Add the following line to the cds.lib file in your ece513 work directory
-{{:wiki:180nm_models_setup.pdf|}}
+<code>
+DEFINE RFIC2013 /home/vsaxena/pdk/models/RFIC2013
+</code>
-<note warning>Note the model location in the slides. Again, we are using NCSU libraries in our setup with 180nm and 1um models. Please don't use alternative setups from other help videos where AMI06 or 0.35um CMOS process were used.</note>
+The cell to use is **ind_scale**. Use the simulation testbench tb_ind_scale to plot s-parameters for the inductor model. Read more in the textbook Chapter 4 on inductor modeling.
-You can see my example schematics by adding the following lines to your cds.lib
+{{:wiki:ind_scale.png?400|}}
-<code>
-/home/vsaxena/ece515/HW1           HW1
-/home/vsaxena/ece515/HW1_180n      HW1_180n
-</code>
 ===== Tutorials =====
 {{:wiki:tutorial_hw1_parametric_sweeps.pdf|I-V and Parametric Sweeps}} - Thanks to Jubayer!
+[[https://www.ece.ucsb.edu/Faculty/rodwell/Classes/ece218c/tutorials_etc/CadenceLNA.pdf|SpectreRF LNA Characterization Tutorial]]

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