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ncsu_180nm_process_info
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ncsu_180nm_process_info [2020/09/03 07:47] vsaxena |
ncsu_180nm_process_info [2020/09/03 13:59] (current) vsaxena [Process Characterization Results] |
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| - | ===== Design Rules and Process Information for the NCSU 180nm CMOS Technology used in the class ===== | + | ===== NCSU 180nm CMOS Process Data ===== |
| - | ===== Process Design Rules ===== | + | ==== Process Design Rules ==== |
| We are using a **0.18 micron 6 Metal 1 Poly** (1.8V) CMOS technology for chip layout. In PDK specific terms, we will use **SUBM_DEEP** design rules with lambda(λ) equal to 0.09 micro meters with Lmin=2λ. Note that this λ is not the channel length modulation parameter! | We are using a **0.18 micron 6 Metal 1 Poly** (1.8V) CMOS technology for chip layout. In PDK specific terms, we will use **SUBM_DEEP** design rules with lambda(λ) equal to 0.09 micro meters with Lmin=2λ. Note that this λ is not the channel length modulation parameter! | ||
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| - | ===== Process Characterization Results ===== | + | ==== Process Data ==== |
| - | The process characterization results are available as: {{ :wiki:tsmc018_info.pdf |}}. You can find numerical values for the various resistances and capacitances in the process. | + | Process characterization results are available as: {{ :wiki:tsmc018_info.pdf |}}. You can find numerical values for the various sheet resistances and capacitances in the process. |
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ncsu_180nm_process_info.1599119221.txt.gz · Last modified: 2020/09/03 07:47 by vsaxena
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