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--- ncsu_180nm_process_info [2020/08/31 06:55]
vsaxena
+++ ncsu_180nm_process_info [2020/09/03 13:59] (current)
vsaxena [Process Characterization Results]
@@ Line 1: / Line 1: @@
-==== Design Rules and Process Information for the NCSU 180nm CMOS Technology used in the class ====
+===== NCSU 180nm CMOS Process Data =====
-  * We will be using an **0.18 micron 6 Metal 1 Poly** (1.8V/3.3V) CMOS technology lambda(λ) equal to 0.09 micro meters. We are using an open-source PDK from NCSU.
+==== Process Design Rules ====
-  * We will use the {{ :wiki:scmos_180nm.pdf | Scalable CMOS}} **SUBM** **design rules** for your CPEG 4/624 layouts. Note that the design rules are given in terms of lambda (=0.09u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.09u for final layout dimensions. E.g. the minimum N-well width of 12 translates into 12*0.09u=1.08u in Virtuoso layout.
+We are using a **0.18 micron 6 Metal 1 Poly** (1.8V) CMOS technology for chip layout. In PDK specific terms, we will use **SUBM_DEEP** design rules with lambda(λ) equal to 0.09 micro meters with Lmin=2λ. Note that this λ is not the channel length modulation parameter!
+The design rules are available as a {{ :wiki:scmos_180nm.pdf | PDF}} and also in [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|Web Browsable Format]].
+Note that the design rules are given in terms of λ while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.09u for final layout dimensions. E.g. the minimum N-well width of 12 translates into 12*0.09u=1.08u in Virtuoso layout.
+-----
+==== Process Data ====
+Process characterization results are available as: {{ :wiki:tsmc018_info.pdf |}}. You can find numerical values for the various sheet resistances and capacitances in the process.
+-----

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