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ncsu_180nm_process_info
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ncsu_180nm_process_info [2020/08/23 03:23] vsaxena created |
ncsu_180nm_process_info [2020/09/03 13:59] (current) vsaxena [Process Characterization Results] |
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| - | ==== Design Rules and Process Information for the 180nm CMOS Technology used in the class ==== | + | ===== NCSU 180nm CMOS Process Data ===== |
| - | * **Design information** for the C5 0.5u process is available [[http://www.mosis.com/vendors/view/on-semiconductor/c5|here]]. | + | ==== Process Design Rules ==== |
| - | * Use the MOSIS Scalable CMOS (SCMOS) **SUBM** **design rules** for your CPEG 4/624 layouts. The design rules can be found in this [[http://www.mosis.com/files/scmos/scmos.pdf|document]]. Note that the design rules are given in terms of lambda (=0.09u) while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.09u for final layout dimensions. Eg. the minimum N-well width of 12 translates into 12*0.09u=1.08u in Virtuoso layout. | + | We are using a **0.18 micron 6 Metal 1 Poly** (1.8V) CMOS technology for chip layout. In PDK specific terms, we will use **SUBM_DEEP** design rules with lambda(λ) equal to 0.09 micro meters with Lmin=2λ. Note that this λ is not the channel length modulation parameter! |
| - | * **Process information** including sheet resistances and transistor parameters can be found {{ :wiki:mosis_ami-c5-params.pdf |here}} . | ||
| + | The design rules are available as a {{ :wiki:scmos_180nm.pdf | PDF}} and also in [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|Web Browsable Format]]. | ||
| - | * **Corner models** for the C5 process are already available on the AMS server. They are usually located on the MOSIS site [[http://www.mosis.com/files/test_data/ami_c5n_corner_bsim3.txt|here]]. | + | Note that the design rules are given in terms of λ while Cadence Virtuoso uses absolute values without any scaling. Thus in your layouts, multiply all design rule numbers by 0.09u for final layout dimensions. E.g. the minimum N-well width of 12 translates into 12*0.09u=1.08u in Virtuoso layout. |
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| + | ----- | ||
| + | ==== Process Data ==== | ||
| + | Process characterization results are available as: {{ :wiki:tsmc018_info.pdf |}}. You can find numerical values for the various sheet resistances and capacitances in the process. | ||
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| + | ----- | ||
ncsu_180nm_process_info.1598152982.txt.gz · Last modified: 2020/08/23 03:23 by vsaxena
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