This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
mixed_signal [2017/04/25 00:51] vsaxena |
mixed_signal [2017/08/19 08:54] (current) vsaxena |
||
|---|---|---|---|
| Line 21: | Line 21: | ||
| <code> | <code> | ||
| + | # NCSU Design Kit Path | ||
| + | CDK_DIR = "/home/vsaxena/pdk/ncsu-cdk-1.6.0.beta" | ||
| + | |||
| # Include basic Spectre and Verilog-A libraries | # Include basic Spectre and Verilog-A libraries | ||
| DEFINE basic $CDSDIR/tools/dfII/etc/cdslib/basic | DEFINE basic $CDSDIR/tools/dfII/etc/cdslib/basic | ||
| Line 27: | Line 30: | ||
| DEFINE sbaLib $CDSDIR/tools/dfII/etc/cdslib/artist/sbaLib | DEFINE sbaLib $CDSDIR/tools/dfII/etc/cdslib/artist/sbaLib | ||
| DEFINE ahdlLib $CDSDIR/tools/dfII/samples/artist/ahdlLib | DEFINE ahdlLib $CDSDIR/tools/dfII/samples/artist/ahdlLib | ||
| - | DEFINE bmslibib $CDSDIR/tools/dfII/samples/artist/bmslib | + | DEFINE bmslib $CDSDIR/tools/dfII/samples/artist/bmslib |
| - | CDK_DIR = "/home/vsaxena/pdk/ncsu-cdk-1.6.0.beta" | ||
| # Include NCSU PDK | # Include NCSU PDK | ||
| DEFINE basic $CDK_DIR/lib/basic | DEFINE basic $CDK_DIR/lib/basic | ||