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cadence_faqs [2020/09/13 02:42]
vsaxena [Virtuoso Layout Editor FAQs]
cadence_faqs [2021/11/03 22:02] (current)
vsaxena
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 **A.** Detailed answer is posted [[why_do_we_use_cadence_or_why_can_t_we_use_other_tools|here.]] **A.** Detailed answer is posted [[why_do_we_use_cadence_or_why_can_t_we_use_other_tools|here.]]
 +----
 **Q.** My schematic and/or layout is locked up and I can't edit it. What should I do? **Q.** My schematic and/or layout is locked up and I can't edit it. What should I do?
  
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 A detailed answer is posted [[removing_cadence_lock_files|here]] A detailed answer is posted [[removing_cadence_lock_files|here]]
 +----
 **Q.** What should I do when prompted for license checkout when using Cadence tools? **Q.** What should I do when prompted for license checkout when using Cadence tools?
  
 **A.** Select the '​Always'​ option. A common rule when using Cadence is 'Never click Never. **A.** Select the '​Always'​ option. A common rule when using Cadence is 'Never click Never.
 +----
 **Q.** What is a **PDK**? **Q.** What is a **PDK**?
  
 **A.** PDK stands for Process Development Kit. Every chip fabrication (fab) service provides a kit that facilitates design, simulation and verification of chips designed using their technology. The PDK consists of Spectre and corner models, Calibre/​Diva extraction data, DRC rules, programmable cells (PCells) and miscellaneous scripts. **A.** PDK stands for Process Development Kit. Every chip fabrication (fab) service provides a kit that facilitates design, simulation and verification of chips designed using their technology. The PDK consists of Spectre and corner models, Calibre/​Diva extraction data, DRC rules, programmable cells (PCells) and miscellaneous scripts.
 +----
 **Q.** Can I purchase and install Cadence on my personal computer? **Q.** Can I purchase and install Cadence on my personal computer?
  
 **A.** No, you can only access it through an X-server client such as X2Go.  **A.** No, you can only access it through an X-server client such as X2Go. 
 +----
  
 ===== Virtuoso Schematic Editor FAQs===== ===== Virtuoso Schematic Editor FAQs=====
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 **A.** This issue arises when you click '​Never'​ when prompted for license checkout. A common rule when working with Cadence is 'Never click Never'​. This option gets saved in a .cdsenv file in your home directory. To fix this issue, delete the .cdsenv file in your home directory (NOT in the local work directory). **A.** This issue arises when you click '​Never'​ when prompted for license checkout. A common rule when working with Cadence is 'Never click Never'​. This option gets saved in a .cdsenv file in your home directory. To fix this issue, delete the .cdsenv file in your home directory (NOT in the local work directory).
 +----
 +**Q.** How do I Add a library so that it shows up in my Library Manager?
 +
 +**A.** In your project directory, open the cds.lib file. Then if you need to add the library /​path/​.../​NewLibrary,​ then add a new line to the cds.lib ​
 +
 +<​code>​DEFINE NewLibrary ​   /​path/​.../​NewLibrary</​code>​
 +
 +Then, in the Library Manager, click View-> Refresh. You should be able to see the NewLibrary added your library.
 +----
 +**Q.** How do I make a copy of a library or a cell?
 +
 +**A.** In the Library Manager, select a library (or cell) and then Right Click and select Copy option. Then you can define the location of the new library (or cell). ​
 +
 +If you are copying library or a hierarchical cell, then its a good idea to update instances of the entire library, so that your schematic uses local copied cells instead of pointing all the time to the original directory.
 +
 +{{:​wiki:​copy_lib.png?​600|}}
 +--------
  
 **Q.** How do I convert Cadence Virtuoso Layout to an image file? **Q.** How do I convert Cadence Virtuoso Layout to an image file?
  
-**A.** [[http://​www.mbeckler.org/​cadence_plot/​|Link]].+**A.** ​Follow the [[http://​www.mbeckler.org/​cadence_plot/​|Link]]. 
 +----
  
 ===== Virtuoso Layout Editor FAQs===== ===== Virtuoso Layout Editor FAQs=====
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 **Q.** How do I get rid of **layout grid errors** when I perform DRC on my layout? **Q.** How do I get rid of **layout grid errors** when I perform DRC on my layout?
  
-**A.** Make sure your major and Minor spacings in layout are multiple of the grid lambda. ​Lets say for 0.5u process the lambda=0.3u, then you change change ​the minor spacings ​to 0.9 and major to 4.5. The grid snap spacing can be 0.15.+**A.** Make sure your major and Minor spacings in layout are multiple of the grid lambda ​(λ). For 0.18um CMOS process the λ=0.09u. You can access the display options by the keystroke/​bindkey “e.” The grid is set to a snap spacing λ/2 (=45nm) in the layout tool. Here, you can set the minor spacing ​to 2λ (=0.18μm) ​and major spacing ​to 10λ (=0.90μm). You should try to size your devices in the integer multiples of λ and place them on the grid to later avoid grid errors.
  
 +----
 **Q.** LVS for my extracted layout doesn'​t work, and shows error in si.log "Diva cannot fine switch master cell .... for instance from viewlist."​ **Q.** LVS for my extracted layout doesn'​t work, and shows error in si.log "Diva cannot fine switch master cell .... for instance from viewlist."​
  
cadence_faqs.1599964926.txt.gz · Last modified: 2020/09/13 02:42 by vsaxena