Differences

This shows you the differences between two versions of the page.

--- cadence_faqs [2014/05/29 16:58]
127.0.0.1 external edit
+++ cadence_faqs [2021/11/03 22:02] (current)
vsaxena
@@ Line 1: / Line 1: @@
-=====Cadence FAQs=====
+===== General Cadence FAQs=====
-  * [[Why do we use Cadence or why can't we use other tools?]]
+**Q.** Why do we use Cadence and not any other software?
+**A.** Detailed answer is posted [[why_do_we_use_cadence_or_why_can_t_we_use_other_tools|here.]]
+----
+**Q.** My schematic and/or layout is locked up and I can't edit it. What should I do?
+**A.** In short, use **clsAdminTool** directly from command terminal. To remove ALL the edit locks in your directory tree, type
+<code> clsAdminTool -are . </code>
+A detailed answer is posted [[removing_cadence_lock_files|here]]
+----
 **Q.** What should I do when prompted for license checkout when using Cadence tools?
 **A.** Select the 'Always' option. A common rule when using Cadence is 'Never click Never.
+----
-**Q.** What is a PDK?
+**Q.** What is a **PDK**?
 **A.** PDK stands for Process Development Kit. Every chip fabrication (fab) service provides a kit that facilitates design, simulation and verification of chips designed using their technology. The PDK consists of Spectre and corner models, Calibre/Diva extraction data, DRC rules, programmable cells (PCells) and miscellaneous scripts.
+----
 **Q.** Can I purchase and install Cadence on my personal computer?
-**A.** No.
+**A.** No, you can only access it through an X-server client such as X2Go.
-==== Schematic Editor ====
+----
-**Q.** I can't open the schematics due to the "licence checkout error".
+===== Virtuoso Schematic Editor FAQs=====
+**Q.** I can't open the schematics due to the **licence checkout error**.
 **A.** This issue arises when you click 'Never' when prompted for license checkout. A common rule when working with Cadence is 'Never click Never'. This option gets saved in a .cdsenv file in your home directory. To fix this issue, delete the .cdsenv file in your home directory (NOT in the local work directory).
+----
+**Q.** How do I Add a library so that it shows up in my Library Manager?
+**A.** In your project directory, open the cds.lib file. Then if you need to add the library /path/.../NewLibrary, then add a new line to the cds.lib
+<code>DEFINE NewLibrary    /path/.../NewLibrary</code>
+Then, in the Library Manager, click View-> Refresh. You should be able to see the NewLibrary added your library.
+----
+**Q.** How do I make a copy of a library or a cell?
+**A.** In the Library Manager, select a library (or cell) and then Right Click and select Copy option. Then you can define the location of the new library (or cell).
+If you are copying library or a hierarchical cell, then its a good idea to update instances of the entire library, so that your schematic uses local copied cells instead of pointing all the time to the original directory.
+{{:wiki:copy_lib.png?600|}}
+--------
+**Q.** How do I convert Cadence Virtuoso Layout to an image file?
+**A.** Follow the [[http://www.mbeckler.org/cadence_plot/|Link]].
+----
-==== Virtuoso Layout ====
+===== Virtuoso Layout Editor FAQs=====
-**Q.** How to get rid of grid errors layout DRC?
-**A.** Make sure your major and Minor spacings in layout are multiple of the grid lambda. Lets say for 0.5u process the lambda=0.3u, then you change change the minor spacings to 0.9 and major to 4.5. The grid snap spacing can be 0.15.
+**Q.** How do I get rid of **layout grid errors** when I perform DRC on my layout?
+**A.** Make sure your major and Minor spacings in layout are multiple of the grid lambda (λ). For 0.18um CMOS process the λ=0.09u. You can access the display options by the keystroke/bindkey “e.” The grid is set to a snap spacing λ/2 (=45nm) in the layout tool. Here, you can set the minor spacing to 2λ (=0.18μm) and major spacing to 10λ (=0.90μm). You should try to size your devices in the integer multiples of λ and place them on the grid to later avoid grid errors.
+----
+**Q.** LVS for my extracted layout doesn't work, and shows error in si.log "Diva cannot fine switch master cell .... for instance from viewlist."
+**A.**  Make sure that in your .bashrc the netlisting mode is set to Analog. You should have the following line in your .bashrc in your home directory. Also, note that these variables are case sensitive.
+<code>
+# Add this line, otherwise LVS will not work
+export CDS_Netlisting_Mode="Analog"
+</code>

Cad Wiki for Analog IC Courses

User Tools

Site Tools

Differences

Page Tools