This shows you the differences between two versions of the page.
| Next revision | Previous revision | ||
|
cad_tutorials_sky130 [2026/08/16 22:14] vsaxena created |
cad_tutorials_sky130 [2026/08/17 06:01] (current) vsaxena |
||
|---|---|---|---|
| Line 3: | Line 3: | ||
| {{:wiki:cadence_logo.png?200|}} | {{:wiki:cadence_logo.png?200|}} | ||
| - | {{ :wiki:cadence_virtuoso_cheat_sheet.pdf |Cadence Bindkeys Cheat Sheet}} | + | {{ :wiki:cadence_virtuoso_cheat_sheet_sky130.pdf |Cadence Bindkeys Cheat Sheet}} |
| - | [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|NCSU PDK Design Rules ]] (html site), {{ :wiki:scmos_180nm.pdf |}} (PDF doc) | + | [[https://skywater-pdk.readthedocs.io/en/main/rules.html|SkyWater SKY130 Process Design Rules]] (html site). |
| - | {{ :wiki:tsmc018_info_v2.pdf | NCSU 180nm CMOS Process Data}} | + | {{https://skywater-pdk.readthedocs.io/en/main/rules/rcx.html | Parasitic Layout Extraction}} |
| + | |||
| + | {{https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html | Device Parameters}} | ||
| ----- | ----- | ||
| Line 18: | Line 20: | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Hierarchical_schematic_opamp/Hierarchical_schematic_opamp.html|Hierarchical Schematic Design: Ideal Opamp Modeling]]. Hierarchical design and simulation. (23:13) | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Hierarchical_schematic_opamp/Hierarchical_schematic_opamp.html|Hierarchical Schematic Design: Ideal Opamp Modeling]]. Hierarchical design and simulation. (23:13) | ||
| - | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/180nm_CMOS_IV_char/180nm_CMOS_IV_char.html|MOSFET I-V Characterization]]: Plot I-V curves for the 180nm CMOS transistors in NCSU PDK. Parametric analysis. Using Calculator tool in ADE-L (26:05) {{ :wiki:180nm_cmos_simulation_setup.pdf |Slides}}. | + | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/180nm_CMOS_IV_char/180nm_CMOS_IV_char.html|MOSFET I-V Characterization]]: Plot I-V curves for the Skywater 130nm CMOS transistors. Parametric analysis. Using Calculator tool in ADE-L {{ :wiki:180nm_cmos_simulation_setup.pdf |Slides}}. |
| - | The 180nm CMOS models are located on the Linux server at <code> /usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta/models/spectre/standalone/tsmc018allModels.scs </code> | + | The Sky130 CMOS models are located on the Linux server at <code> /usa/vsaxena/pdks/ncsu-cdk-1.6.0.beta/models/spectre/standalone/tsmc018allModels.scs </code> |
| ----- | ----- | ||