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cad_tutorials [2022/07/07 21:35] vsaxena [Lab 3: Bias Circuit Design] |
cad_tutorials [2026/08/30 22:49] (current) vsaxena [Lab 5: Layout Basics] |
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| - | ==== Lab 2: Layout Basics ==== | + | ==== Lab 2: Process Characterization and gm/ID Methodology ==== |
| - | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_basics/Layout_basics.html|Layout Basics]]. Layout layers, display options, setting up grid, overview of commands, and DRC rules (24:52) | + | * See the Lab manual. |
| - | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_poly_resistor/Layout_poly_resistor.html|Layout: Poly Resistor]]. Layout of unsilicided poly resistor (10:02) | + | |
| - | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/layout_voltage_divider/layout_voltage_divider.html|Layout: Matched Voltage Divider]]. Design and layout of a matched voltage divider (26:15) | + | |
| - | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_mimcap/Layout_mimcap.html|Layout: MiM Capacitor]]. Layout of a MiM capacitor (12:17) | + | |
| - | ----- | ||
| ==== Lab 3: Bias Circuit Design ==== | ==== Lab 3: Bias Circuit Design ==== | ||
| * See the Lab manual. | * See the Lab manual. | ||
| + | |||
| ==== Lab 4: Diffamp Design ==== | ==== Lab 4: Diffamp Design ==== | ||
| - | * TBD | + | * See the Lab manual. |
| - | ---- | + | ==== Lab 5: Diffamp Design ==== |
| - | ==== CMOS Inverter and Ring Oscillator ==== | + | * See the Lab manual. |
| + | |||
| + | |||
| + | ==== Lab 5: Layout Basics ==== | ||
| + | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_basics/Layout_basics.html|Layout Basics]]. Layout layers, display options, setting up grid, overview of commands, and DRC rules (24:52) | ||
| + | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_poly_resistor/Layout_poly_resistor.html|Layout: Poly Resistor]]. Layout of unsilicided poly resistor (10:02) | ||
| + | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/layout_voltage_divider/layout_voltage_divider.html|Layout: Matched Voltage Divider]]. Design and layout of a matched voltage divider (26:15) | ||
| + | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_mimcap/Layout_mimcap.html|Layout: MiM Capacitor]]. Layout of a MiM capacitor (12:17) | ||
| + | |||
| + | ----- | ||
| + | |||
| + | ==== Lab 6: CMOS Inverter and Ring Oscillator ==== | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_design/cmos_inverter_design.html|CMOS Inverter Design]]. Schematic and layout of a CMOS Inverter {{:wiki:inv_layout.png?40|}} | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_design/cmos_inverter_design.html|CMOS Inverter Design]]. Schematic and layout of a CMOS Inverter {{:wiki:inv_layout.png?40|}} | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_simulation/cmos_inverter_simulation.html|CMOS Inverter Simulation]]. Simulation of the CMOS Inverter | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_simulation/cmos_inverter_simulation.html|CMOS Inverter Simulation]]. Simulation of the CMOS Inverter | ||
cad_tutorials.1657229739.txt.gz · Last modified: 2022/07/07 21:35 by vsaxena
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