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cad_tutorials [2020/12/12 09:04] vsaxena [Project: Create GDS File from Layout] |
cad_tutorials [2026/08/30 22:49] (current) vsaxena [Lab 5: Layout Basics] |
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| {{ :wiki:cadence_virtuoso_cheat_sheet.pdf |Cadence Bindkeys Cheat Sheet}} | {{ :wiki:cadence_virtuoso_cheat_sheet.pdf |Cadence Bindkeys Cheat Sheet}} | ||
| - | [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|NCSU PDK Design Rules ]], {{ :wiki:scmos_180nm.pdf |}} | + | [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|NCSU PDK Design Rules ]] (html site), {{ :wiki:scmos_180nm.pdf |}} (PDF doc) |
| {{ :wiki:tsmc018_info_v2.pdf | NCSU 180nm CMOS Process Data}} | {{ :wiki:tsmc018_info_v2.pdf | NCSU 180nm CMOS Process Data}} | ||
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| - | ==== Lab 2: Layout Basics ==== | + | ==== Lab 2: Process Characterization and gm/ID Methodology ==== |
| + | * See the Lab manual. | ||
| + | |||
| + | ==== Lab 3: Bias Circuit Design ==== | ||
| + | * See the Lab manual. | ||
| + | |||
| + | |||
| + | ==== Lab 4: Diffamp Design ==== | ||
| + | * See the Lab manual. | ||
| + | |||
| + | |||
| + | ==== Lab 5: Diffamp Design ==== | ||
| + | * See the Lab manual. | ||
| + | |||
| + | |||
| + | ==== Lab 5: Layout Basics ==== | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_basics/Layout_basics.html|Layout Basics]]. Layout layers, display options, setting up grid, overview of commands, and DRC rules (24:52) | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_basics/Layout_basics.html|Layout Basics]]. Layout layers, display options, setting up grid, overview of commands, and DRC rules (24:52) | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_poly_resistor/Layout_poly_resistor.html|Layout: Poly Resistor]]. Layout of unsilicided poly resistor (10:02) | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Layout_poly_resistor/Layout_poly_resistor.html|Layout: Poly Resistor]]. Layout of unsilicided poly resistor (10:02) | ||
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| - | ==== Lab 3: CMOS Inverter and Ring Oscillator ==== | + | |
| + | ==== Lab 6: CMOS Inverter and Ring Oscillator ==== | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_design/cmos_inverter_design.html|CMOS Inverter Design]]. Schematic and layout of a CMOS Inverter {{:wiki:inv_layout.png?40|}} | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_design/cmos_inverter_design.html|CMOS Inverter Design]]. Schematic and layout of a CMOS Inverter {{:wiki:inv_layout.png?40|}} | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_simulation/cmos_inverter_simulation.html|CMOS Inverter Simulation]]. Simulation of the CMOS Inverter | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_simulation/cmos_inverter_simulation.html|CMOS Inverter Simulation]]. Simulation of the CMOS Inverter | ||
cad_tutorials.1607763896.txt.gz · Last modified: 2020/12/12 09:04 by vsaxena
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