This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
cad_tutorials [2020/12/11 07:30] vsaxena |
cad_tutorials [2024/06/11 01:15] (current) vsaxena [CMOS Inverter and Ring Oscillator] |
||
|---|---|---|---|
| Line 5: | Line 5: | ||
| {{ :wiki:cadence_virtuoso_cheat_sheet.pdf |Cadence Bindkeys Cheat Sheet}} | {{ :wiki:cadence_virtuoso_cheat_sheet.pdf |Cadence Bindkeys Cheat Sheet}} | ||
| - | [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|NCSU PDK Design Rules ]], {{ :wiki:scmos_180nm.pdf |}} | + | [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|NCSU PDK Design Rules ]] (html site), {{ :wiki:scmos_180nm.pdf |}} (PDF doc) |
| {{ :wiki:tsmc018_info_v2.pdf | NCSU 180nm CMOS Process Data}} | {{ :wiki:tsmc018_info_v2.pdf | NCSU 180nm CMOS Process Data}} | ||
| Line 31: | Line 31: | ||
| ----- | ----- | ||
| - | ==== Lab 3: CMOS Inverter and Ring Oscillator ==== | + | ==== Lab 3: Bias Circuit Design ==== |
| + | * See the Lab manual. | ||
| + | |||
| + | ==== Lab 4: Diffamp Design ==== | ||
| + | * See the Lab manual. | ||
| + | |||
| + | |||
| + | ---- | ||
| + | ==== Digital Lab 1: CMOS Inverter and Ring Oscillator ==== | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_design/cmos_inverter_design.html|CMOS Inverter Design]]. Schematic and layout of a CMOS Inverter {{:wiki:inv_layout.png?40|}} | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_design/cmos_inverter_design.html|CMOS Inverter Design]]. Schematic and layout of a CMOS Inverter {{:wiki:inv_layout.png?40|}} | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_simulation/cmos_inverter_simulation.html|CMOS Inverter Simulation]]. Simulation of the CMOS Inverter | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_simulation/cmos_inverter_simulation.html|CMOS Inverter Simulation]]. Simulation of the CMOS Inverter | ||
| Line 39: | Line 47: | ||
| ---- | ---- | ||
| - | ==== Project: Create GDS File from Layout ==== | + | ==== Project: Create GDS File from Layout === |
| - | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Create_GDS/Create_GDS.html|Create GDS]]. Create GDS file from layout (6:10) | + | * Using the [[Pad Frame]] {{ :wiki:padframe1.png?200 |}} |
| - | Klayout can be downloaded from here. The layermap file for the NCSU PDK is {{ :wiki:tsmc02d.zip |here}} (unzip it before use). | + | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Create_GDS/Create_GDS.html|Create GDS]]. Create GDS file from layout (6:13) |
| + | {{:wiki:180n_layermap.png?300|}} | ||
| + | |||
| + | You can verify your tape-out GDS using **Klayout** which you can download (to be installed on your PC) from [[https://www.klayout.de/build.html|here]]. The layermap file for the tsmc02d technology is {{ :wiki:tsmc02d.zip |here}} (unzip it before use). | ||
| + | |||
| + | ---- | ||
| ==== HW 2 ==== | ==== HW 2 ==== | ||