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cad_tutorials [2020/10/10 03:50] vsaxena |
cad_tutorials [2024/06/11 01:15] (current) vsaxena [CMOS Inverter and Ring Oscillator] |
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| {{ :wiki:cadence_virtuoso_cheat_sheet.pdf |Cadence Bindkeys Cheat Sheet}} | {{ :wiki:cadence_virtuoso_cheat_sheet.pdf |Cadence Bindkeys Cheat Sheet}} | ||
| - | [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|NCSU PDK Design Rules ]], {{ :wiki:scmos_180nm.pdf |}} | + | [[https://www.eecis.udel.edu/~vsaxena/Cadence/SCMOS_rules/MOSIS_Layer_Map_for_SCN6M.html|NCSU PDK Design Rules ]] (html site), {{ :wiki:scmos_180nm.pdf |}} (PDF doc) |
| {{ :wiki:tsmc018_info_v2.pdf | NCSU 180nm CMOS Process Data}} | {{ :wiki:tsmc018_info_v2.pdf | NCSU 180nm CMOS Process Data}} | ||
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| - | ==== Lab 3: CMOS Inverter and Ring Oscillator ==== | + | ==== Lab 3: Bias Circuit Design ==== |
| + | * See the Lab manual. | ||
| + | |||
| + | ==== Lab 4: Diffamp Design ==== | ||
| + | * See the Lab manual. | ||
| + | |||
| + | |||
| + | ---- | ||
| + | ==== Digital Lab 1: CMOS Inverter and Ring Oscillator ==== | ||
| * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_design/cmos_inverter_design.html|CMOS Inverter Design]]. Schematic and layout of a CMOS Inverter {{:wiki:inv_layout.png?40|}} | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_design/cmos_inverter_design.html|CMOS Inverter Design]]. Schematic and layout of a CMOS Inverter {{:wiki:inv_layout.png?40|}} | ||
| - | * [[|CMOS Inverter Simulation]]. Simulation of a CMOS Inverter | + | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/cmos_inverter_simulation/cmos_inverter_simulation.html|CMOS Inverter Simulation]]. Simulation of the CMOS Inverter |
| - | * [[|Ring Oscillator Design]]. Schematic, layout and simulation of a ring oscillator using the CMOS inverter cell {{:wiki:ring_osc_layout.png?100|}} | + | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/ring_oscillator_design/ring_oscillator_design.html|Ring Oscillator Design]]. Schematic, layout and simulation of a ring oscillator using the CMOS inverter cell {{:wiki:ring_osc_layout.png?100|}} |
| * {{ :wiki:using_recursive_nets_in_cadence.pdf| Using Iterative Nets in Cadence}} | * {{ :wiki:using_recursive_nets_in_cadence.pdf| Using Iterative Nets in Cadence}} | ||
| + | |||
| + | ---- | ||
| + | |||
| + | ==== Project: Create GDS File from Layout === | ||
| + | * Using the [[Pad Frame]] {{ :wiki:padframe1.png?200 |}} | ||
| + | * [[https://www.eecis.udel.edu/~vsaxena/Cadence/tutorials/Create_GDS/Create_GDS.html|Create GDS]]. Create GDS file from layout (6:13) | ||
| + | {{:wiki:180n_layermap.png?300|}} | ||
| + | |||
| + | You can verify your tape-out GDS using **Klayout** which you can download (to be installed on your PC) from [[https://www.klayout.de/build.html|here]]. The layermap file for the tsmc02d technology is {{ :wiki:tsmc02d.zip |here}} (unzip it before use). | ||
| ---- | ---- | ||
cad_tutorials.1602301816.txt.gz · Last modified: 2020/10/10 03:50 by vsaxena
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